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CY7C1620KV18 数据表 (PDF) - Cypress Semiconductor

CY7C1620KV18 Datasheet PDF - Cypress Semiconductor
部件名 CY7C1620KV18
下载  CY7C1620KV18 下载

文件大小   753.0 Kbytes
  32 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 144-Mbit DDR II SRAM Two-Word Burst Architecture

CY7C1620KV18 Datasheet (PDF)

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CY7C1620KV18 Datasheet PDF - Cypress Semiconductor

部件名 CY7C1620KV18
下载  CY7C1620KV18 Click to download

文件大小   753.0 Kbytes
  32 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 144-Mbit DDR II SRAM Two-Word Burst Architecture

CY7C1620KV18 数据表 (HTML) - Cypress Semiconductor

Back Button CY7C1620KV18 Datasheet HTML 1Page - Cypress Semiconductor CY7C1620KV18 Datasheet HTML 2Page - Cypress Semiconductor CY7C1620KV18 Datasheet HTML 3Page - Cypress Semiconductor CY7C1620KV18 Datasheet HTML 4Page - Cypress Semiconductor CY7C1620KV18 Datasheet HTML 5Page - Cypress Semiconductor CY7C1620KV18 Datasheet HTML 6Page - Cypress Semiconductor CY7C1620KV18 Datasheet HTML 7Page - Cypress Semiconductor CY7C1620KV18 Datasheet HTML 8Page - Cypress Semiconductor CY7C1620KV18 Datasheet HTML 9Page - Cypress Semiconductor CY7C1620KV18 Datasheet HTML 10Page - Cypress Semiconductor Next Button 

CY7C1620KV18 产品详情

Functional Description
The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. On CY7C1618KV18 and CY7C1620KV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1618KV18 and two 36-bit words in the case of CY7C1620KV18 sequentially into or out of the device.

Features
■ 144-Mbit density (8M × 18, 4M × 36)
■ 333 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
   ❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5-cycle read latency when DOFF is asserted high
■ Operates similar to DDR I device with one cycle read latency when DOFF is asserted low
■ 1.8-V core power supply with high-speed transceiver logic (HSTL) inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–VDD)
   ❐ Supports both 1.5-V and 1.8-V I/O supply
■ Available in 165-ball fine-pitch ball grid array (FBGA) package (15 × 17 × 1.4 mm)
■ Offered in Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement




类似零件编号 - CY7C1620KV18

制造商部件名数据表功能描述
logo
Cypress Semiconductor
CY7C1620KV18-250BZXC CYPRESS-CY7C1620KV18-250BZXC Datasheet
1Mb / 32P
   144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1620KV18-333BZXI CYPRESS-CY7C1620KV18-333BZXI Datasheet
1Mb / 32P
   144-Mbit DDR II SRAM Two-Word Burst Architecture
More results


类似说明 - CY7C1620KV18

制造商部件名数据表功能描述
logo
Cypress Semiconductor
CY7C161KV18 CYPRESS-CY7C161KV18 Datasheet
1Mb / 32P
   144-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1623KV18 CYPRESS-CY7C1623KV18 Datasheet
773Kb / 28P
   144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
CY7C1625KV18 CYPRESS-CY7C1625KV18 Datasheet
894Kb / 33P
   144-Mbit QDR짰 II SRAM Two-Word Burst Architecture
CY7C1518AV18 CYPRESS-CY7C1518AV18_11 Datasheet
1Mb / 29P
   72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1418KV18 CYPRESS-CY7C1418KV18_12 Datasheet
1Mb / 31P
   36-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1316KV18 CYPRESS-CY7C1316KV18 Datasheet
1,019Kb / 32P
   18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1648KV18 CYPRESS-CY7C1648KV18_12 Datasheet
857Kb / 30P
   144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1668KV18 CYPRESS-CY7C1668KV18 Datasheet
771Kb / 30P
   144-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
CY7C1648KV18 CYPRESS-CY7C1648KV18 Datasheet
783Kb / 29P
   144-Mbit DDR II SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1523KV18 CYPRESS-CY7C1523KV18_13 Datasheet
792Kb / 28P
   72-Mbit DDR II SIO SRAM Two-Word Burst Architecture
More results




关于 Cypress Semiconductor


赛普拉斯半导体是一家美国公司,专门从事高性能数字和模拟集成电路(ICS)的设计和制造。
该公司成立于1982年,总部位于美国加利福尼亚州圣何塞。
赛普拉斯(Cypress)提供了广泛的产品,包括微控制器,内存产品,无线连接解决方​​案以及其他数字和模拟IC。
该公司的产品用于各种应用,例如消费电子,汽车系统,工业系统等。
赛普拉斯以其在嵌入式系统领域的混合信号和可编程系统,高质量产品和创新方面的专业知识而闻名。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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