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DM74LS73AM 数据表 (PDF) - Fairchild Semiconductor

DM74LS73AM Datasheet PDF - Fairchild Semiconductor
部件名 DM74LS73AM
下载  DM74LS73AM 下载

文件大小   53.28 Kbytes
  5 Pages
制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
标志 FAIRCHILD - Fairchild Semiconductor
功能描述 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

DM74LS73AM Datasheet (PDF)

Go To PDF Page 下载 数据表
DM74LS73AM Datasheet PDF - Fairchild Semiconductor

部件名 DM74LS73AM
下载  DM74LS73AM Click to download

文件大小   53.28 Kbytes
  5 Pages
制造商  FAIRCHILD [Fairchild Semiconductor]
网页  http://www.fairchildsemi.com
标志 FAIRCHILD - Fairchild Semiconductor
功能描述 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

DM74LS73AM 数据表 (HTML) - Fairchild Semiconductor

DM74LS73AM Datasheet HTML 1Page - Fairchild Semiconductor DM74LS73AM Datasheet HTML 2Page - Fairchild Semiconductor DM74LS73AM Datasheet HTML 3Page - Fairchild Semiconductor DM74LS73AM Datasheet HTML 4Page - Fairchild Semiconductor DM74LS73AM Datasheet HTML 5Page - Fairchild Semiconductor

DM74LS73AM 产品详情

General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the
negative going edge of the clock pulse. The data on the J and K inputs is allowed to change while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated. A low logic level on the clear input will reset the outputs regardless of the levels of the
other inputs.




类似零件编号 - DM74LS73AM

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关于 Fairchild Semiconductor


Fairchild半导体是一家开创性的半导体公司,成立于1950年代后期。
该公司以其在第一个商业晶体管的开发方面的创新而闻名,以及对综合电路技术发展的贡献。
Fairchild成为电力半导体,模拟和混合信号综合电路以及其他半导体产品的领先供应商。
该公司是在2016年被ON半导体收购的,其产品和技术继续在ON半导体品牌下开发和出售。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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