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72V36110L10BBGI8 数据表 (PDF) - Integrated Device Technology

72V36110L10BBGI8 Datasheet PDF - Integrated Device Technology
部件名 72V36110L10BBGI8
下载  72V36110L10BBGI8 下载

文件大小   310.35 Kbytes
  48 Pages
制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology
功能描述 3.3 VOLT HIGH-DENSITY SUPERSYNC II

72V36110L10BBGI8 Datasheet (PDF)

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72V36110L10BBGI8 Datasheet PDF - Integrated Device Technology

部件名 72V36110L10BBGI8
下载  72V36110L10BBGI8 Click to download

文件大小   310.35 Kbytes
  48 Pages
制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology
功能描述 3.3 VOLT HIGH-DENSITY SUPERSYNC II

72V36110L10BBGI8 数据表 (HTML) - Integrated Device Technology

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72V36110L10BBGI8 产品详情

DESCRIPTION:
The IDT72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is
   written to an empty FIFO to the time it can be read, is fixed and short.
• Asynchronous/Synchronous translation on the read or write ports
• High density offerings up to 4 Mbit

FEATURES:
• Choose among the following memory organizations:
   IDT72V36100 - 65,536 x 36
   IDT72V36110 - 131,072 x 36
• Higher density, 2Meg and 4Meg SuperSync II FIFOs
• Up to 166 MHz Operation of the Clocks
• User selectable Asynchronous read and/or write ports (PBGA Only)
• User selectable input and output port bus-sizing
   - x36 in to x36 out
   - x36 in to x18 out
   - x36 in to x9 out
   - x18 in to x36 out
   - x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
   default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost
   Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
   Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (PBGA Only)
• Independent Read and Write Clocks (permit reading and writing
   simultaneously)
• Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic
   Ball Grid Array (PBGA) (with additional features)
• Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/
   72V3670/72V3680/72V3690) family
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information




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关于 Integrated Device Technology


集成设备技术(IDT)是一家美国公司,专门从事混合信号半导体解决方案的设计和制造。
该公司成立于1980年,总部位于加利福尼亚州圣何塞。
IDT提供了广泛的产品,包括时钟和时机解决方案,内存接口和数字逻辑产品。
该公司的产品用于各种应用,例如计算,电信和工业自动化。
IDT以其在混合信号半导体技术方面的专业知识以及向客户提供高质量和可靠产品的能力而闻名。
该公司在世界各地都有运营和设施,并与客户紧密合作,提供符合其特定要求和需求的定制半导体解决方案。
除了其核心业务外,IDT还为汽车,数据中心和物联网(IoT)市场提供解决方案。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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