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CY7C1355A-133AC 数据表 (PDF) - Cypress Semiconductor

CY7C1355A-133AC Datasheet PDF - Cypress Semiconductor
部件名 CY7C1355A-133AC
下载  CY7C1355A-133AC 下载

文件大小   563.4 Kbytes
  28 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

CY7C1355A-133AC Datasheet (PDF)

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CY7C1355A-133AC Datasheet PDF - Cypress Semiconductor

部件名 CY7C1355A-133AC
下载  CY7C1355A-133AC Click to download

文件大小   563.4 Kbytes
  28 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL Architecture

CY7C1355A-133AC 数据表 (HTML) - Cypress Semiconductor

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CY7C1355A-133AC 产品详情

Functional Description
The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. These employ high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of Six transistors.

Features
• Zero Bus Latency, no dead cycles between write and read cycles
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 133, 117, and 100 MHz
• Fast OE access time: 6.5, 7.0, and 7.5ns
• Internally synchronized registered outputs eliminate the need to control OE
• 3.3V –5% and +5% power supply
• 3.3V or 2.5V I/O supply
• Single WEN (READ/WRITE) control pin
• Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte write (BWa–BWd) control (may be tied LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ mode or CE deselect.
• JTAG boundary scan (except CY7C1357A)
• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid Array) for CY7C1355A, and 100-pin TQFP packages for both devices




类似零件编号 - CY7C1355A-133AC

制造商部件名数据表功能描述
logo
Cypress Semiconductor
CY7C1355B CYPRESS-CY7C1355B Datasheet
560Kb / 33P
   9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355B-100AC CYPRESS-CY7C1355B-100AC Datasheet
560Kb / 33P
   9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355B-100AI CYPRESS-CY7C1355B-100AI Datasheet
560Kb / 33P
   9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355B-100BG CYPRESS-CY7C1355B-100BG Datasheet
560Kb / 33P
   9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355B-100BGC CYPRESS-CY7C1355B-100BGC Datasheet
560Kb / 33P
   9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
More results


类似说明 - CY7C1355A-133AC

制造商部件名数据表功能描述
logo
Cypress Semiconductor
CY7C1371B CYPRESS-CY7C1371B Datasheet
876Kb / 26P
   512K x 36/1M x 18 Flow-Thru SRAM with NoBL Architecture
CY7C1354BV25 CYPRESS-CY7C1354BV25 Datasheet
518Kb / 27P
   256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture
CY7C1354A CYPRESS-CY7C1354A Datasheet
546Kb / 31P
   256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture
CY7C1354A CYPRESS-CY7C1354A_04 Datasheet
402Kb / 28P
   256K x 36/512K x 18 Pipelined SRAM with NoBL??Architecture
CY7C1355C CYPRESS-CY7C1355C Datasheet
497Kb / 32P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1355C CYPRESS-CY7C1355C_06 Datasheet
504Kb / 28P
   9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL??Architecture
CY7C1355B-100AC CYPRESS-CY7C1355B-100AC Datasheet
560Kb / 33P
   9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
CY7C1361A CYPRESS-CY7C1361A Datasheet
818Kb / 26P
   256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM
CY7C1354DV25 CYPRESS-CY7C1354DV25 Datasheet
869Kb / 29P
   9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture
CY7C1354CV25 CYPRESS-CY7C1354CV25_06 Datasheet
492Kb / 28P
   9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL??Architecture
More results




关于 Cypress Semiconductor


赛普拉斯半导体是一家美国公司,专门从事高性能数字和模拟集成电路(ICS)的设计和制造。
该公司成立于1982年,总部位于美国加利福尼亚州圣何塞。
赛普拉斯(Cypress)提供了广泛的产品,包括微控制器,内存产品,无线连接解决方​​案以及其他数字和模拟IC。
该公司的产品用于各种应用,例如消费电子,汽车系统,工业系统等。
赛普拉斯以其在嵌入式系统领域的混合信号和可编程系统,高质量产品和创新方面的专业知识而闻名。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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