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CY7C1302DV25 数据表 (PDF) - Cypress Semiconductor

CY7C1302DV25 Datasheet PDF - Cypress Semiconductor
部件名 CY7C1302DV25
下载  CY7C1302DV25 下载

文件大小   231.16 Kbytes
  18 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

CY7C1302DV25 Datasheet (PDF)

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CY7C1302DV25 Datasheet PDF - Cypress Semiconductor

部件名 CY7C1302DV25
下载  CY7C1302DV25 Click to download

文件大小   231.16 Kbytes
  18 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture

CY7C1302DV25 数据表 (HTML) - Cypress Semiconductor

Back Button CY7C1302DV25 Datasheet HTML 1Page - Cypress Semiconductor CY7C1302DV25 Datasheet HTML 2Page - Cypress Semiconductor CY7C1302DV25 Datasheet HTML 3Page - Cypress Semiconductor CY7C1302DV25 Datasheet HTML 4Page - Cypress Semiconductor CY7C1302DV25 Datasheet HTML 5Page - Cypress Semiconductor CY7C1302DV25 Datasheet HTML 6Page - Cypress Semiconductor CY7C1302DV25 Datasheet HTML 7Page - Cypress Semiconductor CY7C1302DV25 Datasheet HTML 8Page - Cypress Semiconductor CY7C1302DV25 Datasheet HTML 9Page - Cypress Semiconductor CY7C1302DV25 Datasheet HTML 10Page - Cypress Semiconductor Next Button 

CY7C1302DV25 产品详情

Functional Description
The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is accomplished through a common address bus.

Features
• Separate independent Read and Write data ports
   — Supports concurrent transactions
• 167-MHz clock for high bandwidth
   — 2.5 ns Clock-to-Valid access time
• 2-word burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz
• Two input clocks (K and K) for precise DDR timing
   — SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.
• Single multiplexed address input bus latches address inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface




类似零件编号 - CY7C1302DV25

制造商部件名数据表功能描述
logo
Cypress Semiconductor
CY7C1302DV25 CYPRESS-CY7C1302DV25 Datasheet
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类似说明 - CY7C1302DV25

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关于 Cypress Semiconductor


赛普拉斯半导体是一家美国公司,专门从事高性能数字和模拟集成电路(ICS)的设计和制造。
该公司成立于1982年,总部位于美国加利福尼亚州圣何塞。
赛普拉斯(Cypress)提供了广泛的产品,包括微控制器,内存产品,无线连接解决方​​案以及其他数字和模拟IC。
该公司的产品用于各种应用,例如消费电子,汽车系统,工业系统等。
赛普拉斯以其在嵌入式系统领域的混合信号和可编程系统,高质量产品和创新方面的专业知识而闻名。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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