GENERAL DESCRIPTION The K522H1HACF is a Multi Chip Package Memory which combines 2G bit NAND Flash and 1G bit Mobile DDR synchronous Dynamic RAM. NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250μs on the (2K+64)Byte page and an erase operation can be performed in typical 2ms on a (128K+4K)Byte block. Data in the data register can be read out at 42ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the device′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. FEATURES <Common> • Operating Temperature : -25°C ~ 85°C • Package : 153ball FBGA Type - 8x9x1.0mmt, 0.5mm pitch <NAND Flash> • Voltage Supply : 1.7V ~ 1.95V • Organization - Memory Cell Array : (256M + 8M) x 8bit for 2Gb (512M + 16M) x 8bit for 4Gb DDP - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (128K + 4K)Byte • Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 40μs(Max.) - Serial Access : 42ns(Min.) • Fast Write Cycle Time - Page Program time : 250μs(Typ.) - Block Erase Time : 2ms(Typ.) • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles with 1bit/512Byte ECC for x8, • Command Driven Operation • Unique ID for Copyright Protection <Mobile DDR SDRAM> • VDD/VDDQ = 1.8V/1.8V • Double-data-rate architecture; two data transfers per clock cycle. • Bidirectional data strobe (DQS). • Four banks operation. • Differential clock inputs (CK and CK). • MRS cycle with address key programs. - CAS Latency (2, 3) - Burst Length (2, 4, 8, 16) - Burst Type (Sequential & Interleave) • EMRS cycle with address key programs. - Partial Array Self Refresh (Full, 1/2, 1/4 Array) - Output Driver Strength Control (Full, 1/2, 1/4, 1/8, 3/4, 3/8, 5/8, 7/8) • Internal Temperature Compensated Self Refresh. • All inputs except data & DM are sampled at the positive going edge of the system clock (CK). • Data I/O transactions on both edges of data strobe, DM for masking. • Edge aligned data output, center aligned data input. • No DLL; CK to DQS is not synchronized. • DM for write masking only. • Auto refresh duty cycle. - 7.8us for -25 to 85 °C • Clock stop capability.
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