General Description
MAX 7000A (including MAX 7000AE) devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture.

Features...
■ High-performance 3.3-V EEPROM-based programmable logic
   devices (PLDs) built on second-generation Multiple Array MatriX
   (MAX®) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in
   IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
   advanced pin-locking capability
   – MAX 7000AE device in-system programmability (ISP) circuitry
      compliant with IEEE Std. 1532
   – EPM7128A and EPM7256A device ISP circuitry compatible with
      IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with
   IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language
   (STAPL) JESD-71
■ Enhanced ISP features
   – Enhanced ISP algorithm for faster programming (excluding
      EPM7128A and EPM7256A devices)
   – ISP_Done bit to ensure complete programming (excluding
      EPM7128A and EPM7256A devices)
   – Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
■ 4.5-ns pin-to-pin logic delays with counter frequencies of up to
   227.3 MHz
■ MultiVoltTM I/O interface enables device core to run at 3.3 V, while
   I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
   (TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space
   saving FineLine BGATM, and plastic J-lead chip carrier (PLCC)
   packages
■ Supports hot-socketing in MAX 7000AE devices
■ Programmable interconnect array (PIA) continuous routing structure
   for fast, predictable performance
■ PCI-compatible
■ Bus-friendly architecture, including programmable slew-rate control
■ Open-drain output option
■ Programmable macrocell registers with individual clear, preset,
   clock, and clock enable controls
■ Programmable power-up states for macrocell registers in
   MAX 7000AE devices
■ Programmable power-saving mode for 50% or greater power
   reduction in each macrocell
■ Configurable expander product-term distribution, allowing up to
   32 product terms per macrocell
■ Programmable security bit for protection of proprietary designs
■ 6 to 10 pin- or logic-driven output enable signals
■ Two global clock signals with optional inversion
■ Enhanced interconnect resources for improved routability
■ Fast input setup times provided by a dedicated path from I/O pin to
   macrocell registers
■ Programmable output slew-rate control
■ Programmable ground pins