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4X16E43V 数据表 (PDF) - List of Unclassifed Manufacturers

4X16E43V Datasheet PDF - List of Unclassifed Manufacturers
部件名 4X16E43V
下载  4X16E43V 下载

文件大小   598.34 Kbytes
  9 Pages
制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers
功能描述 4 MEG x 16 EDO DRAM

4X16E43V Datasheet (PDF)

Go To PDF Page 下载 数据表
4X16E43V Datasheet PDF - List of Unclassifed Manufacturers

部件名 4X16E43V
下载  4X16E43V Click to download

文件大小   598.34 Kbytes
  9 Pages
制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers
功能描述 4 MEG x 16 EDO DRAM

4X16E43V 数据表 (HTML) - List of Unclassifed Manufacturers

4X16E43V Datasheet HTML 1Page - List of Unclassifed Manufacturers 4X16E43V Datasheet HTML 2Page - List of Unclassifed Manufacturers 4X16E43V Datasheet HTML 3Page - List of Unclassifed Manufacturers 4X16E43V Datasheet HTML 4Page - List of Unclassifed Manufacturers 4X16E43V Datasheet HTML 5Page - List of Unclassifed Manufacturers 4X16E43V Datasheet HTML 6Page - List of Unclassifed Manufacturers 4X16E43V Datasheet HTML 7Page - List of Unclassifed Manufacturers 4X16E43V Datasheet HTML 8Page - List of Unclassifed Manufacturers 4X16E43V Datasheet HTML 9Page - List of Unclassifed Manufacturers

4X16E43V 产品详情

[MEMPHIS]

GENERAL DESCRIPTION
The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns on the MEM4X16E43VTW. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 row-address bits (A0-A11) and 10 column-address bits (A0-A9) on the MEM4X16E43VTW version. In addition, the byte and word accesses are supported via the two CAS# pins (CASL# and CASH#).

FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x16 pinout, timing, functions, and package
• 12 row, 10 column addresses (4)
   13 row, 9 column addresses (8)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms
• Self refresh for low-power data retention




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