 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ST72324J2 数据表(PDF) 133 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST72324J2 数据表(HTML) 133 Page - STMicroelectronics |
|
|
133 / 156 page  ST72324J/K 133/156 EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to VDD are not implemented. An additional local protection between the pad and VSS (5a & 5b) is implemented to completely absorb the posi- tive ESD discharge. Multisupply Configuration When several types of ground (VSS, VSSA, ...) and power supply (VDD, VAREF, ...) are available for any reason (better noise immunity...), the structure shown in Figure 79 is implemented to protect the device against ESD. Figure 77. Positive Stress on a True Open Drain Pad vs. VSS Figure 78. Negative Stress on a True Open Drain Pad vs. VDD Figure 79. Multisupply Configuration IN VDD VSS (1) (2b) (4) OUT VDD VSS (3b) Main path Path to avoid (5a) (5b) IN VDD VSS (1) (2b) (4) OUT VDD VSS (3b) Main path (3b) (3b) VAREF VSSA VAREF VDD VSS BACK TO BACK DIODE BETWEEN GROUNDS VSSA |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
