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PIC12LC671 数据表(PDF) 102 Page - Microchip Technology |
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PIC12LC671 数据表(HTML) 102 Page - Microchip Technology |
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102 / 129 page  PIC12C67X DS30561B-page 102 © 1999 Microchip Technology Inc. FIGURE 12-6: CLKOUT AND I/O TIMING TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS Param No. Sym Characteristic Min Typ† Max Units Conditions 10* TosH2ckL OSC1 ↑ to CLKOUT↓ — 75 200 ns Note 1 11* TosH2ckH OSC1 ↑ to CLKOUT↑ — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT ↑ TOSC + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT ↑ 0— — ns Note 1 17* TosH2ioV OSC1 ↑ (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1 ↑ (Q2 cycle) to Port input invalid (I/O in hold time) PIC12C67X 100 — — ns 18A* PIC12LC67X 200 — — ns 19* TioV2osH Port input valid to OSC1 ↑ (I/O in setup time) 0— — ns 20* TioR Port output rise time PIC12C67X — 10 40 ns 20A* PIC12LC67X — — 80 ns 21* TioF Port output fall time PIC12C67X — 10 40 ns 21A* PIC12LC67X — — 80 ns 22††* Tinp GP2/INT pin high or low time TCY —— ns 23††* Trbp GP0/GP1/GP3 change INT high or low time TCY —— ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC. Note: Refer to Figure 12-4 for load conditions. OSC1 CLKOUT I/O Pin (input) I/O Pin (output) Q4 Q1 Q2 Q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value |
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