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STC89LE52RC 数据表(PDF) 126 Page - STCmicro Technology Co,.Ltd |
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STC89LE52RC 数据表(HTML) 126 Page - STCmicro Technology Co,.Ltd |
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126 / 165 page  ISP_CONTR: ISP/IAP Control Register LSB bit B7 B6 B5 B4 B3 B2 B1 B0 name ISPEN SWBS SWRST - - WT2 WT1 WT0 ISPEN : ISP/IAP operation enable. 0 : Global disable all ISP/IAP program/erase/read function. 1 : Enable ISP/IAP program/erase/read function. SWBS: software boot selection control. 0 : Boot from main-memory after reset. 1 : Boot from ISP memory after reset. SWRST: software reset trigger control. 0 : No operation 1 : Generate software system reset. It will be cleared by hardware automatically. Note: Software reset actions could reset other SFR, but it never influence bits ISPEN and SWBS. The ISPEN and SWBS only will reset by power-up action, while not software reset. B3: Reserved. Software must write “0” on this bit when ISP_CONTR is written. WT2~WT0 : Waiting time selection while flash is busy. Setting wait times CPU wait times WT2 WT1 WT0 Read Program <=55uS Sector Erase <=21mS Recommended System Clock Frequency (MHz) 0 1 1 6 SYSclks 30 SYSclks 5471 SYSclks 5MHz 0 1 0 11 SYSclks 60 SYSclks 10942 SYSclks 10MHz 0 0 1 22 SYSclks 120SYSclks 21885SYSclks 20MHz 0 0 0 43 SYSclks 240 SYSclks 43769 SYSclks 40MHz 9.2 STC89xx series internal EEPROM Selection Table STC89xx series MCU internal EEPROM Selection Table Type EEPROM (Byte) Sector Numbers Begin_Sector Begin_Address End_Sector End_Address STC89C/LE51RC 4K 8 0000H 0FFFH STC89C/LE52RC 4K 8 0000H 0FFFH STC89C/LE54RD+ 45K 90 0000H 0B3FFH STC89C/LE58RD+ 29K 58 0000H 73FFH 126 |
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