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ALC5642R-VF-CG 数据表(PDF) 28 Page - Realtek Semiconductor Corp. |
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ALC5642R-VF-CG 数据表(HTML) 28 Page - Realtek Semiconductor Corp. |
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28 / 156 page  ALC5642-VF Datasheet Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzReal TM Digital Sound Effect 16 Rev. 0.93 7.4. Clocking The system clock of ALC5642 can be selected from MCLK or PLL. MCLK is always provided externally while the reference clock of PLL can be selected from MCLK, BCLK1/2. The driver should arrange the clock of each block and setup each divider. The Clk_sys_i2s1=256*Fs provides clocks into stereo DAC/ADC filter that can be selected from MCLK or PLL. Refer to Figure 5. Audio SYSCLK The Clk_sys_i2s2=256*Fs provides clocks into mono DAC/ADC filter that can be selected from MCLK, PLL, refer to Figure 5. Audio SYSCLK When enable ASRC (Asynchronous Sample Rate Converter) function, the clock sources from MCLK and BCLK1 (or BCLK2) are allowed to be asynchronous. The Realtek ASRC technology can ensure data accuracy and keep audio performance under clock source asynchronous. When ALC5642 at master mode, the clock source from MCLK will be divided and be sent to external device. The ratio of BCLK and LRCK can set by register – MX-73. PLL MCLK Clk_sys_i2s1(256FS) (Slave) LRCK1(Slave) MCLK PLL LRCK2 MX80[15:14] MX80[13:12] MX80[3] MX73[14:12] System Clock LRCK1 LRCK1(Master) Master Mode LRCK/BCLK Ratio LRCK2(Slave) LRCK2(Master) BCLK2 BCLK1 BCLK1(Master) BCLK2(Master) DIV_F2 Clk_sys_i2s2(256FS) MX73[10:8] Inter. Clock ÷2 DIV_F1 (Slave) MX70[15] MX71[15] MX70[15] MX71[15] MX81 & MX82 MX73[15] Filter_Clk1 (256FS) Clk_sys_i2s2(256FS) Master Mode LRCK/BCLK Ratio MX73[11] Figure 6. Audio Clock Tree |
类似零件编号 - ALC5642R-VF-CG |
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类似说明 - ALC5642R-VF-CG |
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