STM32MP151AAB3 datasheet(215/253 Pages) STMICROELECTRONICS

215 / 253 page

DS12500 Rev 3

215/253

STM32MP151A/D

Electrical characteristics

232

Figure 46. SPI timing diagram - slave mode and CPHA = 0

tsu(MI)

Data input setup time

Master mode

tsu(SI)

Slave mode

th(MI)

Data input hold time

Master mode

th(SI)

Slave mode

ta(SO)

Data output access time Slave mode

tdis(SO)

Data output disable time Slave mode

7.5

tv(SO)

Data output valid time

Slave mode

2.7 V ≤ VDD ≤ 3.6 V

-11

Slave mode

1.71 V ≤ VDD ≤ 3.6 V

-11

tv(MO)

Master mode

1.5

2.5

th(SO)

Data output hold time

Slave mode

1.71 V ≤ VDD ≤ 3.6 V

th(MO)

Master mode

1. Guaranteed by characterization results.

2. Maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or

high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master

having tsu(MI) = 0 while Duty(SCK) = 50%.

Table 98. SPI dynamic characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv41658V1

NSS input

CPHA=0

CPOL=0

CPHA=0

CPOL=1

MISO output

MOSI input

tsu(SI)

th(SI)

tw(SCKL)

tw(SCKH)

tc(SCK)

tr(SCK)

th(NSS)

tdis(SO)

tsu(NSS)

ta(SO)

tv(SO)

Next bits IN

Last bit OUT

First bit IN

First bit OUT

Next bits OUT

th(SO)

tf(SCK)

Last bit IN

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