AM652X datasheet(159/277 Pages) TI1

159 / 277 page

MCU_PLL0

(MCU PLL)

SPRSP08_PLL_PWR_01

MCU_PLL1

(CPSW PLL)

PLL0

(MAIN PLL)

PLL2

(PER1 PLL)

PLL1

(PER0 PLL)

PLL3

(DDR PLL)

PLL4

(DSS PLL)

PLL6

(ARM0 PLL)

PLL7

(ARM1 PLL)

VDDA_MCU

VDDA_PLL_CORE

VDDA_PLL_PER0

VDDA_PLL0_DDR

VDDA_PLL_DSS

VDDA_PLL_MPU0

VDDA_PLL_MPU1

159

AM6548, AM6528, AM6546

AM6526, AM6527

www.ti.com

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

Figure 5-25 shows the power supply connectivity implemented in the device.

Figure 5-25. PLL Power Supply Connectivity

5.9.4.4

Recommended Clock and Control Signal Transition Behavior

All clocks and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input

transitions are more susceptible to glitches due to noise, and special care must be taken for slow input

clocks.

5.9.4.5

Module and Peripheral Clock Frequencies

The maximum operating frequency associated with module functional and interface clocks internal to the

device is managed by the DMSC firmware. For more details about the clocking structure for a specific

module or peripheral, see Device Configurations chapter in the device TRM.

Section 5.9.5, Peripherals documents the maximum frequency associated with the peripheral clocks in

and out of the device.

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