STM32G47PBY6XXX datasheet(193/229 Pages) STMICROELECTRONICS

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DS12712 Rev 3

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STM32G473xB STM32G473xC STM32G473xE

Electrical characteristics

194

Figure 52. Quad SPI timing diagram - SDR mode

tw(CKH) Quad SPI clock high

and low time

Even division

PRESCALER [7:0]

n =0,1, 3, 5 ...

t(CK)/2

t(CK)/2+1

tw(CKL)

t(CK)/2-1

t(CK)/2

tw(CKH) Quad SPI clock high and

low time

Odd division

PRESCALER [7:0]

n =2,4, 6, 8...

(n/2)*t(CK)/(n+1)

(n/2)*t(CK)/(n+1) + 1

tw(CKL)

(n/2+1)*t(CK)/(n+1) - 1

(n/2+1)*t(CK)/(n+1)

tsr(IN)

Data input setup time on

rising edge

1.71 < VDD< 3.6 V

tsf(IN)

Data input setup time on

falling edge

1.71 < VDD< 3.6 V

thr(IN)

Data input hold time on

rising edge

1.71 < VDD< 3.6 V

thf(IN)

Data input hold time on

falling edge

1.71 < VDD< 3.6 V

tvr(OUT)

Data output valid time on

rising edge

1.71 < VDD< 3.6 V

DHHC = 0

7.5

1.71 < VDD< 3.6 V

DHHC = 1

Thclk/2

Thclk/2+1.5

tvf(OUT) Data output valid time

1.71 < VDD< 3.6 V

DHHC = 0

710

1.71 < VDD< 3.6 V

DHHC = 1

Thclk/2

Thclk/2+2

thr(OUT)

Data output hold time on

rising edge

1.71 < VDD< 3.6 V

DHHC = 0

1.71 < VDD< 3.6 V

DHHC = 1

Thclk/2+ 0.5

thf(OUT)

Data output hold time on

falling edge

1.71 < VDD< 3.6 V

DHHC = 0

1.71 < VDD< 3.6 V

DHHC = 1

Thclk/2+0.5

1. Guaranteed by characterization results.

Table 104. QUADSPI characteristics in DDR mode(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MSv36878V1

Data output

Clock

Data input

t(CK)

tw(CKH)

tw(CKL)

tr(CK)

tf(CK)

ts(IN)

th(IN)

tv(OUT)

th(OUT)

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