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STM32G474PBY3XXX 数据表(PDF) 189 Page - STMicroelectronics |
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STM32G474PBY3XXX 数据表(HTML) 189 Page - STMicroelectronics |
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189 / 236 page  DS12288 Rev 5 189/236 STM32G474xB STM32G474xC STM32G474xE Electrical characteristics 200 Synchronous waveforms and timings Figure 44 through Figure 47 represent synchronous waveforms and Table 102 through Table 105 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable • MemoryType = FMC_MemoryType_CRAM • WriteBurst = FMC_WriteBurst_Enable • CLKDivision = 1 • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period. • For 2.7 V ≤ VDD ≤ 3.6 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 54 MHz for CLKDIV = 0x0 at CL = 30 pF (on FMC_CLK). • For 1.71 V ≤ VDD ≤ 2.7 V, maximum FMC_CLK = 60 MHz for CLKDIV = 0x1 and 32 MHz for CLKDIV = 0x0 at CL= 20 pF (on FMC_CLK). Figure 44. Synchronous multiplexed NOR/PSRAM read timings FMC_CLK FMC_NEx FMC_NADV FMC_A[25:16] FMC_NOE FMC_AD[15:0] AD[15:0] D1 D2 FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKH-NExH) t d(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKH-AIV) td(CLKL-NOEL) td(CLKH-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) MS32757V1 |
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