STM32MP157A datasheet(149/259 Pages) STMICROELECTRONICS

149 / 259 page

DS12504 Rev 5

149/259

STM32MP157A/D

Electrical characteristics

237

Figure 16. High-speed external clock source AC timing diagram (analog bypass)

VPP

OSC_IN peak-to-peak amplitude

0.2(4)

-0.67×VDD

tSU(5)

Time to start

10(6)

µs

tr/tf(HSE)

Rise and Fall time

(10% to 90% threshold levels of the

input peak-to-peak amplitude)

0.05 ×THSE

-0.3 ×THSE

I(HSE)

Power consumption

150(7)

500(8)

µA

1. Guaranteed by design.

2. Guaranteed by design with a square wave signal (@25 °C, VDD=3.3 V /VPP = 400 mV / VDC=1 V) where

VDC is the DC component of the input signal.

3. Guaranteed by design with a square wave signal (@25 °C, VDD=1.71 V /VPP = 200 mV / VDC=0.8 V) where

VDC is the DC component of the input signal.

4. minimum peak-to-peak amplitude (@25 °C, 0.1<VDC<VDD-0.1 V) where VDC is the DC component of the

input signal.

5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized analog

bypass clock interface is reached. This value is measured with 200 mV peak-to-peak amplitude.

6. Maximum start-up time is obtained with 200 mV peak-to-peak amplitude.

7. with a sine wave signal (VPP = 400 mV / VDC=0.4 V) where VDC is the DC component of the input signal.

8. with a sine wave signal (VDD = 3.6 V / VPP = 800 mV / VDC = 1.8 V) where VDC is the DC component of the

input signal.

Table 31. Low-speed external user clock characteristics

(analog bypass)(1)

Symbol

Parameter

Min

Typ

Max

Unit

fLSE_ext

User external clock source frequency

32.768

kHz

VLSE

Absolute input range

VSW(2)

Table 30. High-speed external user clock characteristics

(analog bypass)(1) (continued)

Symbol

Parameter

Min

Typ

Max

Unit

MSv47498V1

VHSE

THSE

VPP

STM32

OSC_IN

fHSE_ext

tr(HSE)

90%

10%

External

clock source

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