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STM32L412R8I6XXX 数据表(PDF) 163 Page - STMicroelectronics |
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STM32L412R8I6XXX 数据表(HTML) 163 Page - STMicroelectronics |
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163 / 192 page ![]() DS12469 Rev 8 163/192 STM32L412xx Electrical characteristics 164 Table 92. QUADSPI characteristics in DDR mode(1) Symbol Parameter Conditions Min Typ Max Unit FCK 1/t(CK) Quad SPI clock frequency 1.71 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 -- 40 MHz 2 < VDD < 3.6 V, CLOAD = 20 pF Voltage Range 1 -- 48 1.71 < VDD < 3.6 V, CLOAD = 15 pF Voltage Range 1 -- 48 1.71 < VDD < 3.6 V CLOAD = 20 pF Voltage Range 2 -- 26 tw(CKH) Quad SPI clock high and low time fAHBCLK = 48 MHz, presc=0 t(CK)/2-2 - t(CK)/2 ns tw(CKL) t(CK)/2 - t(CK)/2+2 tsr(IN) Data input setup time on rising edge Voltage Range 1 1 -- Voltage Range 2 3.5 tsf(IN) Data input setup time on falling edge Voltage Range 1 1 -- Voltage Range 2 1.5 thr(IN) Data input hold time on rising edge Voltage Range 1 6 -- Voltage Range 2 6.5 thf(IN) Data input hold time on falling edge Voltage Range 1 5.5 -- Voltage Range 2 5.5 tvr(OUT) Data output valid time on rising edge Voltage Range 1 - 55.5 Voltage Range 2 9.5 14 tvf(OUT) Data output valid time on falling edge Voltage Range 1 - 58.5 Voltage Range 2 15 19 thr(OUT) Data output hold time on rising edge Voltage Range 1 3.5 - - Voltage Range 2 8 - thf(OUT) Data output hold time on falling edge Voltage Range 1 3.5 - - Voltage Range 2 13 - 1. Guaranteed by characterization results. |
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