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ADIN2111CCPZ-R7 数据表(PDF) 118 Page - Analog Devices |
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ADIN2111CCPZ-R7 数据表(HTML) 118 Page - Analog Devices |
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118 / 125 page  Data Sheet ADIN2111 REGISTERS analog.com Rev. 0 | 118 of 125 Table 235. Bit Descriptions for FC_IRQ_EN Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 FC_IRQ_EN Frame Checker Interrupt Enable. When set, this bit enables the frame checker interrupt. 0x1 R/W Frame Checker Transmit Select Register Device Address: 0x1F; Register Address: 0x8005, Reset: 0x0000, Name: FC_TX_SEL This register is used to select the transmit side or receive side for frames to be checked. If set, frames received from the MAC interface to be transmitted are checked. The frame checker can be used to verify that correct data is received over the MAC interface and is also useful if remote loopback is enabled (see the MAC_IF_REM_LB_EN bit in the MAC_IF_LOOPBACK register) because it can be used to check the received data after it is looped back at the MAC interface. Table 236. Bit Descriptions for FC_TX_SEL Bits Bit Name Description Reset Access [15:1] RESERVED Reserved. 0x0 R 0 FC_TX_SEL Frame Checker Transmit Select. When set, this bit indicates that the frame checker must check frames received to be transmitted by the PHY. 0x0 R/W 1: check frames from the MAC interface to be transmitted by the PHY. 0: check frames received by the PHY from the remote end. Receive Error Count Register Device Address: 0x1F; Register Address: 0x8008, Reset: 0x0000, Name: RX_ERR_CNT The receive error counter register is used to access the receive error counter associated with the frame checker in the PHY. Table 237. Bit Descriptions for RX_ERR_CNT Bits Bit Name Description Reset Access [15:0] RX_ERR_CNT Receive Error Count. This is the receive error counter associated with the frame checker in the PHY. Note that this bit is self clearing upon reading. 0x0 R SC Frame Checker Count High Register Device Address: 0x1F; Register Address: 0x8009, Reset: 0x0000, Name: FC_FRM_CNT_H This register is a latched copy of Bits[31:16] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT) is read, the receive frame counter register is latched so that the error count and the receive frame count are synchronized. Table 238. Bit Descriptions for FC_FRM_CNT_H Bits Bit Name Description Reset Access [15:0] FC_FRM_CNT_H Bits[31:16] of Latched Copy of the Number of Received Frames. 0x0 R Frame Checker Count Low Register Device Address: 0x1F; Register Address: 0x800A, Reset: 0x0000, Name: FC_FRM_CNT_L This register is a latched copy of Bits[15:0] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT) is read, the receive frame counter register is latched so that the error count and receive frame count are synchronized. |
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