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7.10.5.8 GPMC

For more details about features and additional description information on the device General-Purpose Memory

Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Note

GPMC has one or more signals which can be multiplexed to more than one pin. Timing requirements

and switching characteristics defined in this section are only valid for specific pin combinations known

as IOSETs. Valid pin combinations or IOSETs for this interface is shown in Section 6.3.12.1.1.

Table 7-51 presents timing conditions for GPMC.

Table 7-51. GPMC Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

1.65

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

133 MHz Synchronous Mode

140

360

All other modes

140

720

td(Trace Mismatch

Delay)

Propagation delay mismatch across all traces

200

For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the

device TRM.

7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode

Hold time, input wait GPMC_WAIT[j] valid after output clock GPMC_CLK high (th(clkH-waitV))

Table 7-52 and Table 7-53 present timing requirements and switching characteristics for GPMC and NOR Flash -

Synchronous Mode.

Table 7-52. GPMC and NOR Flash Timing Requirements — Synchronous Mode

see Figure 7-39, Figure 7-40, and Figure 7-43

NO.

PARAMETER

DESCRIPTION

MODE(5)

MIN

MAX

MIN

MAX

UNIT

GPMC_FCLK =

100 MHz(2)

GPMC_FCLK =

133 MHz(2)

F12 tsu(dV-clkH)

Setup time, input data

GPMC_AD[n:0](1) valid before

output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.81

1.12

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.06

3.5

F13 th(clkH-dV)

Hold time, input data

GPMC_AD[n:0](1) valid after output

clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.29

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.29

F21 tsu(waitV-clkH)

Setup time, input wait

GPMC_WAIT[j](3) (4) valid before

output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.81

1.12

not_div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

1.06

3.5

AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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