KSZ9567R datasheet(188/232 Pages) MICROCHIP

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KSZ9567R

DS00002329D-page 188

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5.3

Tables and MIB Counters (Access)

Indirect address and data registers are used to access the various tables and counters:

• Address Lookup (ALU) Table

• Static Address Table

• Reserved Multicast Address Table

• VLAN Table

• Access Control List (ACL) Table

• Management Information Base (MIB) Counters

5.3.1

ADDRESS LOOKUP (ALU) TABLE

The Address Lookup Table is the largest of three tables used for MAC address lookup. It supports both dynamic and

static MAC address entries. In response to a destination address (DA) lookup, all tables are searched to make a packet

forwarding decision. In response to a source address (SA) lookup, only this table is searched for aging, migration and

learning of the dynamic entries.

It is suggested that static address entries be programmed to the Static Address Table. When that table is full, additional

static address entries may be programmed into this table. Static entries will not be aged out.

A static DA lookup result (in either this table or the Static Address Table) takes precedence over the dynamic DA lookup

result.

This table is a 4-way associative memory, with 1K buckets, for a total of 4K entries. In normal operation, the MAC

address (and optionally the FID) are hashed to generate a 10-bit index. The 10-bit index specifies a bucket of up to 4

entries, but the entries within each bucket are not individually addressable. A new entry can be added to a bucket if the

bucket contains 3 or fewer valid entries. Once a bucket is full with 4 valid entries, any new entry will overwrite the least-

recently-used dynamic entry.

If a bucket contains 2 or 3 static entries, adding an additional static entry to that bucket will generate an Almost Full

interrupt. (Refer to the Address Lookup Table Interrupt Register and Global Interrupt Status Register). Once the interrupt

is generated, the 12-bit absolute address of the new static entry will be available for reading in the Address Lookup Table

Entry Index 0 Register bits [11:0].

If a bucket is full with 4 static entries, attempting to write an additional static entry will fail and will result in a Write Fail

Interrupt. Once the interrupt is generated, the 10-bit index of the full bucket will be available for reading in the Address

Lookup Table Entry Index 0 Register bits [9:0].

A bucket with 4 static entries will also block any dynamic entries from being learned. Such a failure will generate a Learn

Fail Interrupt. Once the interrupt is generated, the 10-bit index of the full bucket will be available for reading in the

Address Lookup Table Entry Index 1 Register bits [9:0].

This table is accessed indirectly via the ALU Table registers:

• ALU Table Index 0 Register

• ALU Table Index 1 Register

• ALU Table Access Control Register

• ALU Table Entry 1 Register

• ALU Table Entry 2 Register

• ALU Table Entry 3 Register

• ALU Table Entry 4 Register

All static and dynamic entries may be read, but only static entries may be written. Because most of the table entries are

created automatically by hardware address learning, and because the table is 4-way associative, three different meth-

ods are available for accessing the memory:

Lookup by MAC address. This utilizes the same hash tag lookup circuitry that is used for ingress packet forward-

ing lookup. The hash tag algorithm is specified by the Hash Option bits in the Switch Lookup Engine Control 0

Direct addressing (Read or write).

Sequential search, returning all valid entries (Read only).

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