KSZ9567R datasheet(199/232 Pages) MICROCHIP

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DS00002329D-page 199

KSZ9567R

5.3.6.1

MIB Counter Read Operation

Indirect access registers are used to read the MIB counters. Separate access registers are provided for each port via

the Port MIB Control and Status Register and Port MIB Data Register. All MIB Counters are read-clear. The steps for

reading a counter are as follows:

Write the MIB Index to bits [23:16] of the Port MIB Control and Status Register.

Set the MIB Read Enable in bit 25 of the Port MIB Control and Status Register. This step and the previous step

may be done together.

Read the MIB Read Enable / Count Valid in bit 25 of the Port MIB Control and Status Register. A '0' value indi-

cates that the read is complete and the count is valid.

Read the count value from the Port MIB Data Register. For 36-bit counters, counter bits [35:32] are read from the

Port MIB Control and Status Register. The Counter Overflow bit is also found in the Port MIB Control and Status

0x15

TxHiPriorityByte

TX high priority good octet count, including PAUSE packets.

0x16

TxLateCollision

Collision is detected later than 512 bit times into the transmission of a

packet.

0x17

TxPausePkts

PAUSE frames transmitted. PAUSE is EtherType (0x8808), DA, control

opcode (0x0001), minimum 64 byte data length, and a valid CRC.

0x18

TxBroadcastPkts

TX good broadcast packets. Does not include erred broadcast packets or

valid multicast packets.

0x19

TxMulticastPkts

TX good multicast packets. Does not include MAC control frames, erred

multicast packets, or valid broadcast packets.

0x1A

TxUnicastPkts

TX good unicast packets.

0x1B

TxDeferred

TX packets where the first transmit attempt is delayed due to the busy

medium.

0x1C

TxTotalCollision

TX total collisions. Half duplex only.

0x1D

TxExcessiveCollision

TX fails due to excessive collisions.

0x1E

TxSingleCollision

Successfully transmitted frames where transmission is inhibited by

exactly one collision.

0x1F

TxMultipleCollision

Successfully transmitted frames where transmission is inhibited by more

than one collision.

0x80

RxByteCnt

RX byte count.

0x81

TxByteCnt

TX byte count.

0x82

RxDropPackets

RX packets dropped due to lack of resources.

0x83

TXDropPackets

TX packets dropped due to lack of resources.

TABLE 5-6:

MIB COUNTERS (CONTINUED)

MIB

Index

MIB Counter

Size

(bits)

Description

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