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KSZ9567R 数据表(PDF) 174 Page - Microchip Technology |
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KSZ9567R 数据表(HTML) 174 Page - Microchip Technology |
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174 / 232 page ![]() KSZ9567R DS00002329D-page 174 2017-2019 Microchip Technology Inc. 5.2.7.8 Port Police Queue Rate Register 5.2.7.9 Port Police Queue Burst Size Register 5.2.7.10 Port WRED Packet Memory Control Register 0 Address: 0xN820 - 0xN823 Port N: 1-7 Size: 32 bits Bits Description Type Default 31:16 Committed Information Rate Specifies the committed information rate for the connection from the Queue Pointer of the port pointed by the Port index. R/W 0x1000 15:0 Peak Information Rate Specifies the queue’s peak information rate for the connection from the Queue Pointer of the port pointed by the Port index. R/W 0x2000 Address: 0xN824 - 0xN827 Port N: 1-7 Size: 32 bits Bits Description Type Default 31:16 Committed Burst Size Specifies the queue’s committed burst size in bytes that is supported for the connection from the Queue Pointer of the port pointed by the Port index. R/W 0x1000 15:0 Peak Information Rate Specifies the queue’s peak burst size in bytes that is supported for the con- nection from the Queue Pointer of the port pointed by the Port index. R/W 0x3000 Address: 0xN830 - 0xN833 Port N: 1-7 Size: 32 bits Bits Description Type Default 31:27 RESERVED RO 00000b 26:16 WRED Packet Memory Maximum Threshold R/W 0x400 15:11 RESERVED RO 00000b 10:0 WRED Packet Memory Minimum Threshold R/W 0x080 |
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