LS009.0
1997.01.16
RTL8029AS Preliminary
7
4. PIN DESCRIPTIONS
4.1. Signal Type Definition
P
Power pins include VDD and GND.
I
Input is a standard input-only signal.
O
It indicates output signal.
T/S
Tri-State is a bi-directional, tri-state input/output pin.
S/T/S
Sustained Tri-State is an active low tri-state signal owned and driven by one and
only one agent at a time. The agent that drives an S/T/S pin low must drive it high
for at least one clock before letting it float.
O/D
Open Drain allowed multiple device to share as a wire-OR.
4.2. Power Pins
No.
Name
Type
Description
22, 39, 52,
75, 85, 100
VDD
P
+5V DC power
11, 17, 34,
48, 72, 80,
91
GND
P
Ground
4.3. PCI Bus Interface Pins
No.
Name
Type
Descriptions
90
CLK
I
Bus Clock provides timing for all transactions on PCI and
is an input pin to every PCI device. All bus signals are
sampled on the rising edge of CLK and all parameters are
defined with respect to this edge.
92-99, 3-
10, 20, 21,
23-28, 30-
33, 35-38
AD31-0
T/S
Address/Data are multiplexed on the same PCI pins. A bus
transaction consists of an address phase followed by one or
more data phases. The address phase is the clock cycle in
which FRAMEB is asserted. During data phase AD7-0
contain the least significant byte(lsb) and AD31-24 contain
the most significant byte(msb). Write data is stable and
valid when IRDYB is asserted and read data is stable and
valid when TRDYB is asserted.
1, 12, 19,
29
CBE3-0B
T/S
Bus Command/Byte Enables are multiplexed on the same
PCI pins. During the address phase of a transaction, CBE3-
0B define the Bus Command. During the data phase CBE3-
0B are used as Byte Enables. The Byte Enables define
which physical byte lanes carry meaning data. CBE0B
applies to byte 0(lsb) and CBE3B applies to byte 3(msb).
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