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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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ST7FL19F1MATRE 数据表(PDF) 128 Page - STMicroelectronics |
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ST7FL19F1MATRE 数据表(HTML) 128 Page - STMicroelectronics |
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128 / 138 page  ST7L15, ST7L19 128/138 FLASH OPTION BYTES (cont’d) OPT 1 = WDGSW Hardware or Software Watch- dog 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) OPT 0 = WDG HALT Watchdog Reset on Halt This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No reset generation when entering HALT mode 1: Reset generation when entering HALT mode Table 25. List of Valid Option Combinations Operating conditions Option Bits VDD range Clock Source PLL Typ fCPU OSC PLLOFF PLLx4x8 3.0 to 3.6V Internal RC 1% off 1 MHz @ 3.3V 0 11 x4 4 MHz @ 3.3V 0 0 x8 - - - - External clock or resonator (depending on OPT5:4 selection) off 0 to 4 MHz 1 11 x4 4 MHz 0 0 x8 - - - - 4.5 to 5.5V Internal RC 1% off 1 MHz @ 5V 0 1 1 x4 - - - - x8 8 MHz @ 5V 0 0 1 External clock or resonator (depending on OPT5:4 selection) off 0 to 8 MHz 1 1 1 x4 - - - - x8 8 MHz 1 0 1 |
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