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AT83SND1CXXX-ROTIL 数据表(PDF) 102 Page - ATMEL Corporation |
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AT83SND1CXXX-ROTIL 数据表(HTML) 102 Page - ATMEL Corporation |
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102 / 212 page  102 4109J–8051–10/06 AT8xC51SND1C Bit Number Bit Mnemonic Description 7DIR Control Endpoint Direction Bit This bit is relevant only if the endpoint is configured in Control type. Set for the data stage. Clear otherwise. Note: This bit should be configured on RXSETUP interrupt before any other bit is changed. This also determines the status phase (IN for a control write and OUT for a control read). This bit should be cleared for status stage of a Control Out transaction. 6 RXOUTB1 Received OUT Data Bank 1 for Endpoints 1 and 2 (Ping-pong mode) This bit is set by hardware after a new packet has been stored in the endpoint FIFO data bank 1 (only in Ping-pong mode). Then, the endpoint interrupt is triggered if enabled and all the following OUT packets to the endpoint bank 1 are rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous Endpoints. This bit should be cleared by the device firmware after reading the OUT data from the endpoint FIFO. |
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