STPMIC25BPQR datasheet(129/145 Pages) STMICROELECTRONICS

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6.8.25

NVM fail-safe shadow register 2 (NVM_FS_SHR2)

Table 105. NVM_FS_SHR2

TSHDN_FLT_CNT_MAX[3:0]

OCP_FLT_CNT_MAX[3:0]

R/W

•

Address: 0xB2

•

Default: Depends on the PMIC part number

•

Description: NVM fail-safe shadow register 2 (see Section 5.4.5).

[7:4]

TSHDN_FLT_CNT_MAX[3:0]: setting of the maximum number of occurrences triggered by a thermal shutdown hard-

fault source.

0000: 0 hard-faults allowed (the PMIC goes in FAIL_SAFE_LOCK_STATE when the 1st hard-fault condition occurs)

0001: 1 hard-fault allowed (the PMIC goes in FAIL_SAFE_LOCK_STATE when the 2nd hard-fault condition occurs)

…

1110: 14 hard-faults allowed (the PMIC goes in FAIL_SAFE_LOCK_STATE when the 15th hard-fault condition occurs)

1111: ∞ hard-faults allowed (fail-safe disabled: the PMIC always restarts when a hard-fault condition occurs)

[3:0]

OCP_FLT_CNT_MAX[3:0]: setting of the maximum number of occurrences triggered by regulator overcurrent hard-fault

source.

0000: 0 hard-faults allowed (the PMIC goes in FAIL_SAFE_LOCK_STATE when the 1st hard-fault condition occurs)

0001: 1 hard-fault allowed (the PMIC goes in FAIL_SAFE_LOCK_STATE when the 2nd hard-fault condition occurs)

…

1110: 14 hard-faults allowed (the PMIC goes in FAIL_SAFE_LOCK_STATE when the 15th hard-fault condition occurs)

1111: ∞ hard-faults allowed (fail-safe disabled: the PMIC always restarts when a hard-fault condition occurs)

STPMIC25

DS14278 - Rev 3

page 129/145

STPMIC25BPQR 数据表(PDF) 129 Page - STMicroelectronics