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ST10F269Z2T3 数据表(PDF) 105 Page - STMicroelectronics |
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ST10F269Z2T3 数据表(HTML) 105 Page - STMicroelectronics |
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105 / 184 page ![]() ST10F269 16 - REAL TIME CLOCK 105/184 16 - REAL TIME CLOCK The Real Time Clock is an independent timer, which clock is directly derived from the clock oscillator on XTAL1 input so that it can keep on running even in Idle or Power down mode (if enabled to). Registers access is implemented onto the XBUS. This module is designed for the following purposes: – Generate the current time and date for the system – Cyclic time based interrupt, provides Port 2 external interrupts every second and every n seconds (n is programmable) if enabled. – 58-bit timer for long term measurement – Capable to exit the ST10 chip from power down mode (if PWDCFG of SYSCON set) after a pro- grammed delay. The real time clock is base on two main blocks of counters. The first block is a prescaler which generates a basic reference clock (for example a 1 second period). This basic reference clock is coming out of a 20-bit DIVIDER (4-bit MSB RTCDH counter and 16-bit LSB RTCDL counter). This 20-bit counter is driven by an input clock derived from the on-chip high frequency CPU clock, predivided by a 1/64 fixed counter (see Figure 51). This 20-bit counter is loaded at each basic reference clock period with the value of the 20-bit PRESCALER register (4-bit MSB RTCPH register and 16-bit LSB RTCPL register). The value of the 20-bit RTCP register determines the period of the basic reference clock. A timed interrupt request (RTCSI) may be sent on each basic reference clock period. The second block of the RTC is a 32-bit counter (16-bit RTCH and 16-bit RTCL). This counter may be initialized with the current system time. RTCH/RTCL counter is driven with the basic reference clock signal. In order to provide an alarm function the contents of RTCH/RTCL counter is compared with a 32-bit alarm register (16-bit RTCAH register and 16-bit RTCAL register). The alarm register may be loaded with a reference date. An alarm interrupt request (RTCAI), may be generated when the value of RTCH/RTCL counter matches the reference date of RTCAH/RTCAL register. The timed RTCSI and the alarm RTCAI interrupt requests can trigger a fast external interrupt via EXISEL register of port 2 and wake-up the ST10 chip when running power down mode. Using the RTCOFF bit of RTCCON register, the user may switch off the clock oscillator when entering the power down mode. Figure 50 : ESFRs and Port Pins Associated with the RTC -- -- - - - - YYYY ---- EXISEL EXISEL External Interrupt Source Selection register (Port 2) 1 second timed interrupt request (RTCSI) triggers firq[2] and alarm interrupt request (RTCAI) triggers firq[3] RTC data and control registers are implemented onto the XBUS. -- -- - - - - YYYYYYYY CCxIC |
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