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STM32F412RGY6PTR 数据表(PDF) 141 Page - STMicroelectronics |
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STM32F412RGY6PTR 数据表(HTML) 141 Page - STMicroelectronics |
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141 / 201 page  DocID028087 Rev 7 141/201 STM32F412xE/G Electrical characteristics 166 6.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 72 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 16. Table 72. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply VDDA −VREF+ < 1.2 V 1.7(1) -3.6 V VREF+ Positive reference voltage 1.7(1) -VDDA V fADC ADC clock frequency VDDA = 1.7(1) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V 0.6 30 36 MHz fTRIG(2) External trigger frequency fADC = 30 MHz, 12-bit resolution - - 1764 kHz -- - 17 1/fADC VAIN Conversion voltage range(3) - 0 (VSSA or VREF- tied to ground) -VREF+ V RAIN(2) External input impedance See Equation 1 for details -- 50 k Ω RADC(2)(4) Sampling switch resistance - - - 6 k Ω CADC(2) Internal sample and hold capacitor -- 4 7 pF tlat(2) Injection trigger conversion latency fADC = 30 MHz - - 0.100 µs -- - 3(5) 1/fADC tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 µs -- - 2(5) 1/fADC tS(2) Sampling time fADC = 30 MHz 0.100 - 16 µs - 3 - 480 1/fADC tSTAB(2) Power-up time - - 2 3 µs tCONV(2) Total conversion time (including sampling time) fADC = 30 MHz 12-bit resolution 0.50 - 16.40 µs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 µs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 µs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 µs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 1/fADC |
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