STM32F412RGU7PTR datasheet(164/201 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F412xE/G

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DocID028087 Rev 7

6.3.26

SD/SDIO MMC/eMMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 96 for the SDIO are derived from

tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage

conditions summarized in Table 16, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output

characteristics.

Table 95. Synchronous non-multiplexed PSRAM write timings(1)(2)

1. CL = 30 pF.

2. Based on characterization, not tested in production.

Symbol

Parameter

Min

Max

Unit

tw(CLK)

FSMC_CLK period

2THCLK – 0.5

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)

td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2)

THCLK + 0.5

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low

td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high

td(CLKL-AV)

FSMC_CLK low to FSMC_Ax valid (x=16…25)

td(CLKH-AIV)

FSMC_CLK high to FSMC_Ax invalid (x=16…25)

THCLK

td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low

1.5

td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high

THCLK + 0.5

td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low

td(CLKL-NBLL) FSMC_CLK low to FSMC_NBL low

td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high

THCLK

tsu(NWAIT-

CLKH)

FSMC_NWAIT valid before FSMC_CLK high

th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high

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