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STM32F412RGY7PTR 数据表(PDF) 161 Page - STMicroelectronics

部件名 STM32F412RGY7PTR
功能描述  Arm®-Cortex®-M4 32b MCUFPU, 125 DMIPS, 1MB Flash, 256KB RAM, USB OTG FS, 17 TIMs, 1 ADC, 17 comm. interfaces
PDF  201 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F412RGY7PTR 数据表(HTML) 161 Page - STMicroelectronics

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DocID028087 Rev 7
161/201
STM32F412xE/G
Electrical characteristics
166
Table 93. Synchronous multiplexed PSRAM write timings(1)(2)
1. CL = 30 pF.
2. Based on characterization, not tested in production.
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FSMC_CLK period, VDD range= 2.7 to 3.6 V
2THCLK - 0.5
-
ns
td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x= 0...2)
-
1
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2)
THCLK + 0.5
-
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low
-
1
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high
0
-
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
-
2
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax invalid (x=16…25)
THCLK
-
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
-
1.5
t(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high
THCLK + 0.5
-
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
-
2.5
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
0
-
td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low
-
4
td(CLKL-NBLL) FSMC_CLK low to FSMC_NBL low
-
3
td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high
THCLK
-
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high
2
-
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high
2
-



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