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STM32F412RGT6TR 数据表(PDF) 125 Page - STMicroelectronics |
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STM32F412RGT6TR 数据表(HTML) 125 Page - STMicroelectronics |
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125 / 201 page  DocID028087 Rev 7 125/201 STM32F412xE/G Electrical characteristics 166 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 14). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating ΣIVSS (see Table 14). Output voltage levels Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 16. All I/Os are CMOS and TTL compliant. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 36 and Table 59, respectively. Table 58. Output voltage characteristics Symbol Parameter Conditions Min Max Unit VOL(1) 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 14. and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Output low level voltage for an I/O pin CMOS port(2) IIO = +8 mA 2.7 V ≤ VDD ≤ 3.6 V 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. -0.4 V VOH(3) 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage for an I/O pin VDD–0.4 - VOL (1) Output low level voltage for an I/O pin TTL port(2) IIO =+8 mA 2.7 V ≤ VDD ≤ 3.6 V -0.4 V VOH (3) Output high level voltage for an I/O pin 2.4 - VOL(1) Output low level voltage for an I/O pin IIO = +20 mA 2.7 V ≤ VDD ≤ 3.6 V -1.3(4) 4. Guaranteed by characterization results, not tested in production. V VOH(3) Output high level voltage for an I/O pin VDD–1.3(4) - VOL(1) Output low level voltage for an I/O pin IIO = +6 mA 1.8 V ≤ VDD ≤ 3.6 V -0.4(4) V VOH(3) Output high level voltage for an I/O pin VDD–0.4(4) - VOL(1) Output low level voltage for an I/O pin IIO = +4 mA 1.7 V ≤ VDD ≤ 3.6 V -0.4(5) 5. Guaranteed by design, not tested in production. V VOH(3) Output high level voltage for an I/O pin VDD–0.4(5) - |
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