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STM32F412RGH6 数据表(PDF) 159 Page - STMicroelectronics |
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STM32F412RGH6 数据表(HTML) 159 Page - STMicroelectronics |
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159 / 201 page ![]() DocID028087 Rev 7 159/201 STM32F412xE/G Electrical characteristics 166 Table 92. Synchronous multiplexed NOR/PSRAM read timings(1)(2) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - 0.5 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 td(CLKH_NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2) THCLK + 0.5 - td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 2 td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x=16…25) THCLK - td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 1.5 td(CLKH-NOEH) FSMC_CLK high to FSMC_NOE high THCLK - td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 2.5 td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 1 - th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 2 - tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 2 - th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 2 - |
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