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STM32F412RGY3 数据表(PDF) 124 Page - STMicroelectronics |
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STM32F412RGY3 数据表(HTML) 124 Page - STMicroelectronics |
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124 / 201 page ![]() Electrical characteristics STM32F412xE/G 124/201 DocID028087 Rev 7 All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT and TC I/Os is shown in Figure 35. Figure 35. FT/TC I/O input characteristics 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 56: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 56: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization, not tested in production. |
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