数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

STM32F429NET6XXX 数据表(PDF) 138 Page - STMicroelectronics

部件名 STM32F429NET6XXX
功能描述  ARM Cortex-M4 32b MCUFPU, 225DMIPS, up to 2MB Flash/2564KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 20 comm. interfaces, camera & LCD-TFT
PDF  231 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F429NET6XXX 数据表(HTML) 138 Page - STMicroelectronics

Back Button STM32F429NET6XXX Datasheet HTML 134Page - STMicroelectronics STM32F429NET6XXX Datasheet HTML 135Page - STMicroelectronics STM32F429NET6XXX Datasheet HTML 136Page - STMicroelectronics STM32F429NET6XXX Datasheet HTML 137Page - STMicroelectronics STM32F429NET6XXX Datasheet HTML 138Page - STMicroelectronics STM32F429NET6XXX Datasheet HTML 139Page - STMicroelectronics STM32F429NET6XXX Datasheet HTML 140Page - STMicroelectronics STM32F429NET6XXX Datasheet HTML 141Page - STMicroelectronics STM32F429NET6XXX Datasheet HTML 142Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 138 / 231 page
background image
Electrical characteristics
STM32F427xx STM32F429xx
138/231
DocID024030 Rev 6
6.3.18
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 56: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.
Figure 37. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 59. Otherwise the reset is not taken into account by the device.
Table 59. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent resistor(1)
VIN = VSS
30
40
50
k
Ω
VF(NRST)(2) NRST Input filtered pulse
-
-
100
ns
VNF(NRST)(2) NRST Input not filtered pulse
VDD > 2.7 V
300
-
-
ns
TNRST_OUT Generated reset pulse duration
Internal Reset source
20
-
-
µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum
(~10% order)
.
2. Guaranteed by design.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com