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STM32F427NET7TR 数据表(PDF) 149 Page - STMicroelectronics |
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STM32F427NET7TR 数据表(HTML) 149 Page - STMicroelectronics |
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149 / 231 page  DocID024030 Rev 6 149/231 STM32F427xx STM32F429xx Electrical characteristics 192 Figure 46. ULPI timing diagram Table 69. USB HS clock timing parameters(1) 1. Guaranteed by design. Symbol Parameter Min Typ Max Unit fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz FSTART_8BIT Frequency (first transition) 8-bit ±10% 54 60 66 MHz FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz DSTART_8BIT Duty cycle (first transition) 8-bit ±10% 40 50 60 % DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025 % tSTEADY Time to reach the steady state frequency and duty cycle after the first transition -- 1.4 ms tSTART_DEV Clock startup time after the de-assertion of SuspendM Peripheral - - 5.6 ms tSTART_HOST Host - - - tPREP PHY preparation time after the first transition of the input clock -- - µs |
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