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STM32F429NET7 数据表(PDF) 155 Page - STMicroelectronics |
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STM32F429NET7 数据表(HTML) 155 Page - STMicroelectronics |
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155 / 231 page  DocID024030 Rev 6 155/231 STM32F427xx STM32F429xx Electrical characteristics 192 The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. a Table 75. ADC static accuracy at fADC = 18 MHz Symbol Parameter Test conditions Typ Max(1) 1. Guaranteed by characterization results. Unit ET Total unadjusted error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V ±3 ±4 LSB EO Offset error ±2 ±3 EG Gain error ±1 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±2 ±3 Table 76. ADC static accuracy at fADC = 30 MHz Symbol Parameter Test conditions Typ Max(1) 1. Guaranteed by characterization results. Unit ET Total unadjusted error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA − VREF < 1.2 V ±2 ±5 LSB EO Offset error ±1.5 ±2.5 EG Gain error ±1.5 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±1.5 ±3 Table 77. ADC static accuracy at fADC = 36 MHz Symbol Parameter Test conditions Typ Max(1) 1. Guaranteed by characterization results. Unit ET Total unadjusted error fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA − VREF < 1.2 V ±4 ±7 LSB EO Offset error ±2 ±3 EG Gain error ±3 ±6 ED Differential linearity error ±2 ±3 EL Integral linearity error ±3 ±6 Table 78. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions Min Typ Max Unit ENOB Effective number of bits fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 °C 10.3 10.4 - bits SINAD Signal-to-noise and distortion ratio 64 64.2 - dB SNR Signal-to-noise ratio 64 65 - THD Total harmonic distortion − 67 − 72 - 1. Guaranteed by characterization results. |
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