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STM32F429NET7 数据表(PDF) 188 Page - STMicroelectronics |
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STM32F429NET7 数据表(HTML) 188 Page - STMicroelectronics |
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188 / 231 page  Electrical characteristics STM32F427xx STM32F429xx 188/231 DocID024030 Rev 6 6.3.27 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 106 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data formats: 14 bits Figure 75. DCMI timing diagram 2. Guaranteed by characterization results. Table 106. DCMI characteristics Symbol Parameter Min Max Unit Frequency ratio DCMI_PIXCLK/fHCLK -0.4 DCMI_PIXCLK Pixel clock input - 54 MHz DPixel Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2 - ns th(DATA) Data input hold time 2.5 - tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 0.5 - th(HSYNC) th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 1 - |
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