STM32L412R8Y6PTR datasheet(156/192 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32L412xx

156/192

DS12469 Rev 4

6.3.24

Communication interfaces characteristics

I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification and user

manual rev. 03 for:

•

Standard-mode (Sm): with a bit rate up to 100 kbit/s

•

Fast-mode (Fm): with a bit rate up to 400 kbit/s

•

Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly

configured (refer to RM0394 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and

SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS

connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins

support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O

port characteristics for the I2C I/Os characteristics.

All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog

filter characteristics:

Table 87. IWDG min/max timeout period at 32 kHz (LSI)(1)

1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there

is always a full RC period of uncertainty.

Prescaler divider

PR[2:0] bits

Min timeout RL[11:0]=

0x000

Max timeout RL[11:0]=

0xFFF

Unit

0.125

512

0.250

1024

/16

0.500

2048

/32

1.0

4096

/64

2.0

8192

/128

4.0

16384

/256

6 or 7

8.0

32768

Table 88. WWDG min/max timeout value at 80 MHz (PCLK)

Prescaler

WDGTB

Min timeout value

Max timeout value

Unit

0.0512

3.2768

0.1024

6.5536

0.2048

13.1072

0.4096

26.2144

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