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STM32MP151AAB3T 数据表(PDF) 175 Page - STMicroelectronics |
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STM32MP151AAB3T 数据表(HTML) 175 Page - STMicroelectronics |
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175 / 245 page  DS12500 Rev 1 175/245 STM32MP151A Electrical characteristics 228 Synchronous waveforms and timings Figure 27 through Figure 30 represent synchronous waveforms and Table 62 through Table 65 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable • MemoryType = FMC_MemoryType_CRAM • WriteBurst = FMC_WriteBurst_Enable • CLKDivision = 1 • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Table 60. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 5Tfmc_ker_ck-0.5 5Tfmc_ker_ck+1 ns tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck-0.5 Tfmc_ker_ck+1 tw(NWE) FMC_NWE low time 2Tfmc_ker_ck-1 2Tfmc_ker_ck+0.5 th(NE_NWE) FMC_NWE high to FMC_NE high hold time 2Tfmc_ker_ck-0.5 - tv(A_NE) FMC_NEx low to FMC_A valid - 0.5 tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 1 tw(NADV) FMC_NADV low time Tfmc_ker_ck+0.5 Tfmc_ker_ck+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck+0.5 - th(A_NWE) Address hold time after FMC_NWE high Address held until next write operation - th(BL_NWE) FMC_BL hold time after FMC_NWE high 3Tfmc_ker_ck+0.5 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck+4 th(Data_NWE) Data hold time after FMC_NWE high 3Tfmc_ker_ck+0.5 - 1. Guaranteed by characterization results. Table 61. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 9Tfmc_ker_ck-0.5 9Tfmc_ker_ck+0.5 ns tw(NWE) FMC_NWE low time 6Tfmc_ker_ck-0.5 6Tfmc_ker_ck+1 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 8Tfmc_ker_ck+4 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 6Tfmc_ker_ck - 1. Guaranteed by characterization results. |
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