IS25LEG-RGLA2:P-TY datasheet(137/193 Pages) ISSI

部件名	IS25LEG-RGLA2:P-TY

功能描述	SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	193 Pages

Scroll/Zoom	100%

制造商	ISSI [Integrated Silicon Solution, Inc]

网页	http://www.issi.com

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137 / 193 page

IS25LE01GG

IS25WE01GG

Integrated Silicon Solution, Inc.- www.issi.com

137

Rev. A3

10/02/2025

Figure 8.92 FRQDTR Sequence In SPI Mode (EDh [EXTADD=1] or EEh, 4-byte address)

CE #

SCK

Instruction = EDh/EEh

CE #

SCK

4-byte Address

High Impedance

...

Mode 3

Mode 0

28 24 20

5 1

29 25 21

Data

Out

...

4 0

IO0

IO1

IO0

30 26 22

31 27 23

16 12 8

17 13 9

18 14 10

19 15 11

6 Dummy Cycles

IO2

IO3

IO1

IO2

IO3

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

5 1

4 0

6 2

7 3

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

Data

Out

5 1

4 0

6 2

7 3

Mode Bits

5 1

4 0

6 2

7 3

...

Notes:

1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode

bits are different from AXh, the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.

3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles

are same, then X should be Hi-Z.

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