AM261...ZFG datasheet(139/218 Pages) TI2

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GPMC_FCLK

GPMC_CLK

GPMC_CSn[i]

GPMC_A[27:17]

GPMC_BE0n_CLE

GPMC_BE1n

GPMC_ADVn_ALE

GPMC_WEn

GPMC_AD[15:0]

GPMC_WAIT[j]

Address (MSB)

Valid Address (LSB)

Data OUT

FA0

FA1

FA9

FA10

FA3

FA25

FA29

FA12

FA27

FA28

FA0

FA10

GPMC_11

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-36. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word

6.11.5.7.6 GPMC/NAND Flash Timing Requirements - Asynchronous Mode 100MHz

(4)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

GNF12(1)

tacc(d)

Access time, GPMC0_AD[31:0](3)

J(2)

(1)

The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2)

J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)

(3)

GPMC_FCLK is general-purpose memory controller internal functional clock.

(4)

100MHz GPMC_FCLK selected - CTRLMMR_GPMC_CLKSEL[0] CLK_SEL = 1 = MAIN_PLL2_HSDIV7_CLKOUT (100/60 MHz)

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AM2612, AM2611, AM2611-Q1, AM2612-Q1

SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025

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AM261...ZFG 数据表(PDF) 139 Page - Texas Instruments

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