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AM261...ZFG 数据表(PDF) 156 Page - Texas Instruments |
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AM261...ZFG 数据表(HTML) 156 Page - Texas Instruments |
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156 / 218 page  Data transmit and receive timing parameters are not defined for the data training use case since they are dynamically adjusted based on the operating condition. 6.11.5.13.2.1.1 OSPI DLL Delay Mapping for PHY Data Training MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE Transmit All modes PHY_CONFIG_TX_DLL_DELAY_FLD (1) Receive All modes PHY_CONFIG_RX_DLL_DELAY_FLD (2) (1) Transmit DLL delay value determined by training software (2) Receive DLL delay value determined by training software 6.11.5.13.2.1.2 OSPI Timing Requirements - PHY Data Training NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O15 tsu(D-LBCLK) Setup time, OSPI_D[7:0] valid before active OSPI_DQS edge DDR with DQS (1) ns O16 th(LBCLK-D) Hold time, OSPI_D[7:0] valid after active OSPI_DQS edge DDR with DQS (1) ns (1) Minimum setup and hold time requirements for OSPI_D[7:0] inputs are not defined when Data Training is used to find the optimum data valid window. tO16t tO16t O15 O15 OSPI_DQS OSPI_D[i:0] Figure 6-49. . OSPI Timing Requirements – PHY Data Training, DDR with DQS 6.11.5.13.2.1.3 OSPI Switching Characteristics - PHY Data Training NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O1 tc(CLK) Cycle time, OSPI_CLK 1.8V, DDR 6.024 ns 3.3V, DDR 7.52 ns O2 tw(CLKL) Pulse duration, OSPI_CLK low DDR 0.475P(1) - 0.3 ns O3 tw(CLKH) Pulse duration, OSPI_CLK high DDR 0.475P(1) - 0.3 ns O4 td(CSn-CLK) Delay time, OSPI_CSn[1:0] active edge to OSPI_CLK rising edge DDR 0.475P(1) + (0.975 × M(2) × R(4)) + 0.35TD(5) - 1 0.525P(1) + (1.025 × M(2) × R(4)) + 0.95TD(5) + 1 ns O5 td(CLK-CSn) Delay time, OSPI_CLK rising edge to OSPI_CSn[1:0] inactive edge DDR 0.475P(1) + (0.975 × N(3) × R(4)) - 0.35TD(5) - 1 0.525P(1) + (1.025 × N(3) × R(4)) - 0.95TD(5) + 1 ns O6 td(CLK-D) Delay time, OSPI_CLK active edge to OSPI_D[7:0] transition DDR (6) (6) ns (1) P = OSPI_CLK cycle time = SCLK period in ns (2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD] (3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (4) R = REFCLK cycle time in ns (5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD AM2612, AM2611, AM2611-Q1, AM2612-Q1 SPRSPA7C – SEPTEMBER 2024 – REVISED JULY 2025 www.ti.com 156 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: AM2612 AM2611 AM2611-Q1 AM2612-Q1 |
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