ST7LITE29 datasheet(113/131 Pages) STMICROELECTRONICS

113 / 131 page

ST7LITE2

113/131

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

TA = -40°C to 125°C, unless otherwise specified

Figure 88. Typical Application with RESET pin 6)7)8)

Notes:

1. Data based on characterization results, not tested in production.

2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin between

VILmax and VDD

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets especially in noisy en-

vironments.

6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in section 13.9.1 on page 113. Otherwise the reset will not be taken into account internally.

8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-

ified for IINJ(RESET) in section 13.2.2 on page 92.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

0.3xVDD

VIH

Input high level voltage

0.7xVDD

Vhys

Schmitt trigger voltage hysteresis 1)

VOL

Output low level voltage 2)

VDD=5V

IIO=+5mA TA≤85°C

TA≥85°C

0.5

1.0

1.2

IIO=+2mA TA≤85°C

TA≥85°C

0.2

0.4

0.5

RON

Pull-up equivalent resistor 3) 1)

VDD=5V

Ω

VDD=3V.

120

tw(RSTL)out Generated reset pulse duration

Internal reset sources

µs

th(RSTL)in External reset pulse hold time

µs

tg(RSTL)in Filtered glitch duration

200

RON

0.01

µF

VDD

0.01

µF

EXTERNAL

RESET

CIRCUIT 5)

USER

VDD

4.7k

Ω

Required if LVD is disabled

Recommended

if LVD is disabled

ST72XXX

PULSE

GENERATOR

Filter

WATCHDOG

LVD RESET

INTERNAL

RESET

VDD

ST7LITE29 数据表(PDF) 113 Page - STMicroelectronics

ST7LITE29 数据表(HTML) 113 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载