ST7LITE29 datasheet(124/131 Pages) STMICROELECTRONICS

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ST7LITE2

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OPTION BYTES (Cont’d)

OPTION BYTE 1

OPT7 = PLLx4x8

PLL Factor selection.

0: PLLx4

1: PLLx8

OPT6 = PLLOFF

PLL disable.

0: PLL enabled

1: PLL disabled (by-passed)

OPT5 = PLL32OFF

32MHz PLL disable.

0: PLL32 enabled

1: PLL32 disabled (by-passed)

OPT4 = OSC

RC Oscillator selection

0: RC oscillator on

1: RC oscillator off

Note: 1% RC oscillator available on ST7LITE25

and ST7LITE29 devices only

OPT3:2 = LVD[1:0]

Low voltage detection selec-

tion

These option bits enable the LVD block with a se-

lected threshold as shown in Table 22.

Table 22. LVD Threshold Configuration

Each device is available for production in a user

programmable version (FLASH). FLASH devices

are shipped to customers with a default content

(FFh). This implies that FLASH devices have to be

configured by the customer using the Option

Bytes.

OPT1 = WDG SW

Hardware or Software

Watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT0 = WDG HALT

Watchdog Reset on Halt

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

Table 23. List of valid option combinations

Note 1: Configuration available on ST7LITE25 and ST7LITE29 devices only

Note: see Clock Management Block diagram in Figure 13

Configuration

LVD1 LVD0

LVD Off

Highest Voltage Threshold (

∼4.1V)

Medium Voltage Threshold (

∼3.5V)

Lowest Voltage Threshold (

∼2.8V)

Operating conditions

Option Bits

VDD range

Clock Source

PLL

Typ fCPU

OSC

PLLOFF

PLLx4x8

2.4V - 3.3V

Internal RC 1%1)

off

0.7MHz @3V

2.8MHz @3V

External clock or oscillator

(depending on OPT6:4 selec-

tion)

off

0-4MHz

4MHz

3.3V - 5.5V

Internal RC 1% 1)

off

1MHz @5V

8MHz @5V

External clock or oscillator

(depending on OPT6:4 selec-

tion)

off

0-8MHz

8 MHz

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