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LC4128V-5T128C 数据表(PDF) 7 Page - Lattice Semiconductor |
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LC4128V-5T128C 数据表(HTML) 7 Page - Lattice Semiconductor |
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7 / 99 page  Lattice Semiconductor ispMACH 4000V/B/C/Z Family Data Sheet 7 Table 5. Product Term Expansion Capability Every time the super cluster allocator is used, there is an incremental delay of tEXP. When the super cluster alloca- tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus- ter is steered to M (n+4), then M (n) is ground). Macrocell The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro- grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions. Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable delay in this path allows designers to choose between the fastest possible set-up time and zero hold time. Figure 5. Macrocell Enhanced Clock Multiplexer The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The eight sources for the clock multiplexer are as follows: • Block CLK0 • Block CLK1 Expansion Chains Macrocells Associated with Expansion Chain (with Wrap Around) Max PT/ Macrocell Chain-0 M0 → M4 → M8 → M12 → M0 75 Chain-1 M1 → M5 → M9 → M13 → M1 80 Chain-2 M2 → M6 → M10 → M14 → M2 75 Chain-3 M3 → M7 → M11 → M15 → M3 70 Single PT Block CLK0 Block CLK1 Block CLK2 Block CLK3 PT Clock (optional) Shared PT Clock CE D/T/L Q RP Shared PT Initialization PT Initialization/CE (optional) PT Initialization (optional) From Logic Allocator Power-up Initialization To ORP To GRP From I/O Cell Delay |
类似零件编号 - LC4128V-5T128C |
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类似说明 - LC4128V-5T128C |
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