 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
H8S/2240 数据表(PDF) 349 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H8S/2240 数据表(HTML) 349 Page - Renesas Technology Corp |
|
|
349 / 818 page  Section 9 16-Bit Timer Pulse Unit (TPU) Rev.3.00 Mar. 26, 2007 Page 307 of 772 REJ09B0355-0300 9.2.4 Timer Interrupt Enable Register (TIER) 7 TTGE 0 R/W 6 — 1 — 5 — 0 — 4 TCIEV 0 R/W 3 TGIED 0 R/W 0 TGIEA 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W Bit Initial value R/W : : : Channel 0: TIER0 7 TTGE 0 R/W 6 — 1 — 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 — 0 — 0 TGIEA 0 R/W 2 — 0 — 1 TGIEB 0 R/W Channel 1: TIER1 Channel 2: TIER2 Bit Initial value R/W : : : The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has three TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby mode. Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE Description 0 A/D conversion start request generation disabled (Initial value) 1 A/D conversion start request generation enabled Bit 6—Reserved: Read-only bit, always read as 1. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
