H8SSLASH2240 datasheet(372/818 Pages) RENESAS

部件名	H8S/2240

功能描述	Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series

PDF	818 Pages

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制造商	RENESAS [Renesas Technology Corp]

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.3.00 Mar. 26, 2007 Page 330 of 772

REJ09B0355-0300

Examples of Buffer Operation

When TGR is an output compare register: Figure 9.19 shows an operation example in which

PWM mode 1 has been designated for channel 0, and buffer operation has been designated for

TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1

output at compare match A, and 0 output at compare match B.

As buffer operation has been set, when compare match A occurs the output changes and the value

in buffer register TGRC is simultaneously transferred to timer general register TGRA. This

operation is repeated each time compare match A occurs.

For details of PWM modes, see section 9.4.5, PWM Modes.

TCNT value

TGR0B

H'0000

TGR0C

Time

TGR0A

H'0200

H'0520

TIOCA

H'0200

H'0450

H'0520

H'0450

TGR0A

H'0450

H'0200

Transfer

Figure 9.19 Example of Buffer Operation (1)

H8S/2240 数据表(PDF) 372 Page - Renesas Technology Corp