H8SSLASH2240 datasheet(394/818 Pages) RENESAS

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Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.3.00 Mar. 26, 2007 Page 352 of 772

REJ09B0355-0300

9.7

Usage Notes

Note that the kinds of operation and contention described below occur during TPU operation.

Module Stop Mode Setting

TPU operation can be disabled or enabled using the module stop control register. The initial

setting is for TPU operation to be halted. Register access is enabled by clearing module stop

mode. For details, refer to section 18, Power-Down Modes.

Input Clock Restrictions

The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at

least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a

narrower pulse width.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.44 shows the input clock

conditions in phase counting mode.

Overlap

Phase

differ-

ence

Phase

differ-

ence

Overlap

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Pulse width

Notes: Phase difference and overlap : 1.5 states or more

Pulse width

: 2.5 states or more

Figure 9.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

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