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H8S/2240 数据表(PDF) 430 Page - Renesas Technology Corp |
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H8S/2240 数据表(HTML) 430 Page - Renesas Technology Corp |
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430 / 818 page ![]() Section 11 Watchdog Timer Rev.3.00 Mar. 26, 2007 Page 388 of 772 REJ09B0355-0300 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the WDT. Overflow Interrupt control WOVI (interrupt request signal) WDTOVF Internal reset signal* Reset control RSTCSR TCNT TSCR φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Clock Clock select Internal clock sources Bus interface Module bus Legend: TCSR TCNT RSTCSR Note: * : Timer control/status register : Timer counter : Reset control/status register WDT The type of internal reset signal depends on a register setting. Either power-on reset or manual reset can be selected. Figure 11.1 Block Diagram of WDT |
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